1. Field of the Invention
The present invention relates generally to microprocessor circuits, and more specifically to internal clocks in microprocessor circuits.
2. Background Information
The instability of the internal clock of a microprocessor can cause numerous problems. For example, uncertainty in the ideal period duration can result in temporal clock cycle shrink which limits critical paths. Furthermore, uncertainty in phase time can affect half-cycle paths. As the speeds of microprocessors increase, these types of problems take on greater significance.
These problems are attributable to clock jitter, which is caused and exacerbated by various factors. For example, the internal clock in a microprocessor is inherently subject to variation caused by power supply noise modulating the delay of the clock distribution network. The systematic accumulated/response error from the PLL/clock generator further increases the uncertainty of the clock edge.
As the internal clock period and high/low times are distorted, a reduction occurs in the time available for critical paths in some clock cycles or half-cycles; this reduction causes a reduction in the maximum operating frequency of the circuit. Measurement of on-chip jitter is hampered by flip-chip packages that are difficult to probe. Clock jitter can be driven off chip via buffers, but the buffers are also subject to the same delay variations that cause the clock jitter. Because on-chip jitter is purely internal to a chip and chips are becoming more complex, this type of jitter is becoming more difficult to observe accurately with existing devices and techniques.
Thus, what is desired is an apparatus and method for detecting and measuring internal clock jitter.